Developments in MOS integrated circuit fabrication technology are continuously achieving reduced device size, and, particularly, reduced gate channel lengths, which are now typically about 0.6 micron and below.
In a conventional process of fabricating MOS integrated circuits, patterned layers of photoresist, such as KTI photoresists, are formed over layers of polysilicon and silicon oxide, such that those portions of the polysilicon layers, and sometimes the oxide layer, not covered by the photoresist are selectively removed in a subsequent etching step in a manner well known to those skilled in the art. The remaining features form the gates of the transistors on the device. Plasma etching has been proven to be particularly useful as an anisotropic etchant.
In an ideal process, the photoresist walls and the underlying polysilicon layers that are produced by the etching are perfectly vertical. It has been found, however, that during an etching process the etchant gas, which typically includes chlorine or a chloride, reacts with the carbon in the photoresist and the polysilicon layers, forming a material which is deposited along the walls, thereby creating sloping sidewalls. The width of the slope from the vertical wall at the substrate surface is termed the polysilicon "etch delta". The deposited material that results in the polysilicon etch delta for chlorine plasma chemistries is denoted CCl.sub.x or SiCl.sub.4, respectively. However, because SiCl.sub.4 is volatile, much of this residue is actually removed by reaction with the etchant gas during the etching process.
This formation of etch delta in the polysilicon sidewalls requires additional spacing between adjacent devices and thus reduces integration density. Moreover, when the process is used to fabricate integrated circuits of different layouts and dimensions, involving differing percentages of photoresist mask areas, different amounts of polysilicon etch delta are developed, which produce corresponding differences in channel lengths.
One approach that has been proposed to reduce the formation of polysilicon etch delta and decrease its sensitivity to pattern density involves the use of an oxide layer patterned by the use of a photoresist mask to form an oxide hard mask. The oxide hard mask is then used to pattern the underlying polysilicon layer. Those concerned with the development of integrated circuit processing have, however, continually sought improved methods of patterning.